p e dl620q 53x_ 54x _55x - 0 6 issue da te j u ly 30,2015 ml62 0q 53x/ 54 x /q55 x ( x:6,8) preliminary ultra low power 16 - bit microcontroller 1 /9 general description this lsi family is a high - performance 16 - bit cm os microcontroller into which rich peripheral circuits, such as synchronous serial port, uart, i2c bus interface (master), supply voltage level detect circuit, rc oscillation type a/d conve rter, and successive approximation type a/d converter are incorpora ted around 16 - bit cpu nx - u16/100. the cpu nx - u16/100 is capable of efficient instruction execution in 1 - instruction 1 - clock mode by 3 - stage pipe line architecture parallel processing. the r ich peripheral circuits such as i/o port, serial interface and time rs are installed. so this lsi family is most suitable for consumer and industry devices that are required for multi - actuation system. and, this lsi has a data flash - memory fill area by software which can be written in. the on - chip debug function that is installed enables program debugging and programming. features ? cpu ? 16- bit risc cpu (cpu name: nx - u16/100) ? instruction system: 16- bit instructions ? instruction set: transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit operation , bit logic operations, jump, conditional jump, ca ll return stack operation , arithmetic shift, and so on . ? on - chip debugs function ? minimum instruction execution time 30.5 s ( @ 32.768 khz system clock) 62.5 ns (@16 mhz system clock) ? built - in coprocessor for multiplication, division, and multiply - accumulate operations ? signed or unsigned operation setting ? multiplication: 16 bit x 16 bit (operation time 4 cycl es) ? division : 32 bit / 16 bit (operation time 8 cycles) ? division: 32 bit / 32 bit (operation time 16 cycles ) ? multiply - accumulate (non - saturating) : 16 bit x 16 bit + 32bit (operation time 4 cycles) ? multiply - accumulate (saturating): 16 bit x 16 bit + 32 bit (operation time 4 cycles) ? internal memory ? supports isp function (re - writing the program memory area by software) ? number of segments product name flash memory sram status program area * data area ml620q558 256kb (128k 16bit) 2kb (1k 16bit) 20kb (10k 16bit) under develop ing ml620q556 128kb (64k 16bit) 2kb (1k 16bit) 10kb (5k 16bit) under p lanning ml620q5 48 256kb (128k 16bit) 2kb (1k 16bit) 20kb (10k 16bit) under p lanning ml620q546 128kb (64k 16bit) 2kb (1k 16bit) 10kb (5k 16bit) under developing ml620q5 38 256kb (128k 16bit) 2kb (1k 16bit) 20kb (10k 16bit) under p lanning ml620q5 36 128kb (64k 16bit) 2kb (1k 16bit) 10kb (5k 16bit) under p lanning *: including 1kb of unusable test area ? interrupt controller (intc) ? 1 non - makeable inter rupt sources (internal source: wdt ) ? 5 2 makeable interrupt sources (internal sources: 4 4 , external sources: 8) ? external interrupts and comparator allow edg e selection and sampling selection ? priority level (4 - level) can be set for each interrupt
p e dl620q 53x_ 5 4 x _5 5 x - 0 6 ml620q 53x/ 54 x / 55 x 2 /9 ? time base counter (tbc) ? low - speed time base counter 2 channel s (1 channel is for real time clock) ? g enerate 32khz~1hz signal by dividing low - speed clock(3 2.768khz) ? interruption generates function, frequency correct function. ? timers (tmr) ? 8 bits 12 channels (timer0 - b : available 16- bit x 6 configuration by using timer0 - 1 or timer2 - 3, timer4 - 5, timer6 - 7, timer8 - 9, timer a - b ) ? se lection of one shot timer mode is available . ? external clock can be selected as timer clock. ? function timers (ftm) ? 16- bit 8 channels ? 4 operation mode [timer mode] function as 16 - bit timer [capture mode] available input signal pulse width and pe riod measurement . [pwm1 mode] available 2 - duty pwm output by 1 ch annel [pwm2 mode] available 1 pair (positive phase/ negative phase) pwm output ? output logic switch function (positive logic/negative logic) ? interrupt generate ( period/duty/ca pture/accord with setting) ? sequential/one shot mode ? available dead time s e tting ? an event trigger (external pin input interrupt or timer interrupt request) can control start/stop/clear of the timer ? available external input emergency stop and emergency stop int errupt ? 3 - phase motor pwm asynchronous pwm (triangle wave modulation 3 - phase pwm ) x 1 ch annel (pwm: 6 output) available dead time s e tting ? watchdog timer (wdt) ? non - makeable interrupts and resets (generate interrupt at 1st overflow, generate reset at 2nd overflow) ? free ru nning ? overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s when lsclk = 32.768 khz) ? watchdog timer status flag active/inactive watchdog timer active detection function(display active sta tus) ? real time clock (rtc) ? 1 ch annel (calendar (u p to 99 years), alarm, time adjustment, 1hz clock output) ? automatic leap year correction ? regular interrupts (0.5s, 1s, 1 minute,) ? alarm interrupt 2 channels (day of the week, hour, minute; month, day hour, minute) ? synchronous serial port (ssiof ) ? with 4 - byte transmits and receives fifos (ssiof) : 2 channel s ? master/ s lave selectable ? lsb first/msb first selectable ? 8 - bit length/16 - bit length s are selectable ? phase/polarity of clock is selectable ? supports slave - select signal ? uart /uart - f ? without fifos (uart) : 1ch ? with 4 - byte s transmits and receives fifos (uartf) : 4ch ? full duplex buffer system ? communication speed: settable within the range of 2400bps to 115200bps. ? programmable interface ( data length, parity, stop bits selecta ble) ? bit length, parity/no parity, odd/even parity, 1/2 stop bit selectable ? positive logic/negative logic selectable ? lin bus correspondence is possible by software ? build - in baud rate generator
p e dl620q 53x_ 5 4 x _5 5 x - 0 6 ml620q 53x/ 54 x / 55 x 3 /9 ? i 2 c bus interface (i 2 c) ? master function 2 channel ? fast mode (400 kbps), standard mode (100 kbps) ? general - purpose ports (port) ? input port 2, input/output port 88 channels (including secondary or tertiary or fourthly or fifthly functions) on ml620q 556/ 558 . ? input port 2, input/out put port 68 channels (including secondary or tertiary or fourthly or fifthly functions) on ml620q54 6 /548 . ? input port 2, input/output port 5 0 channels (including secondary or tertiary or fourthly or fifthly functions) on ml620q5 36 /538 . ? melody d river (melody) ? tempo: 15 types ? scale: 29 types (melody sound frequency: 508 hz to 10.922 khz) ? tone length: 63 types ? buzzer output mode (4 output modes, 8 buzzer frequencies, 7duty levels at 4.096khz /15 duty levels at other buzzer frequencies) ? r c oscillation type a/d converter (rc - adc) ? time division 2 channels ? 24- bit counter ? successive approximation type a/d converter (sa - adc) ? input 20 channels on ml620q558/556/548/546 input 16 channels on ML620Q538/536 ? c onversion time : 1.25 us ? 10- bit a/d converter ? starting by trigger of timer/ftm function ? analog comparator (cmp) ? input x 2 ch annel ? operation voltage range: vdd = 1.8v ~ 5.5v ? common mode input voltage : 0.2v to v dd 0.2v ? input offset voltage : 30mv(max) ? interrupt al low edge selection and sampling are selectable ? voltage level supervisor (vls) ? threshold voltages: selectable from 16 levels ? interrupt or reset generate are s e lectable ? low level detector(lld) ? judgment voltage: 1.8v 0.2v ? a vailable low level det ecction reset generation. ? reset ? reset by the reset_n pin ? reset by power - on detection ? reset by overflow of watchdog timer (wdt) ? reset by voltage level supervisor(vls) ? reset by low level detector(lld) ? clock ? low - speed clock: (this lsi canno t guarantee the operation without low - speed clock) crystal oscillation (32.768 khz) external clock input (30khz to 36khz) built - in rc oscillation (32.768khz) d etects the stop of the crystal oscillation and automatically change to built - in rc oscillation ? high - speed clock: crystal / ceramic oscillation (16mhz)
p e dl620q 53x_ 5 4 x _5 5 x - 0 6 ml620q 53x/ 54 x / 55 x 4 /9 external clock input (300 khz to 16 mhz) built - in rc oscillation (16mhz) ? flash programming ? supports remap function software remap, hardware remap ? in self programming ( isp) ? power management ? halt mode: instruction execution by cpu is suspended. all peripheral circuits keep operating states. ? halt - h mode: instruction execution by cpu is suspended. stop of high - speed oscillation automatically. all peripheral circuits keep operating states. ? d eep - halt mode: instruction execution by cpu is suspended. some peripheral circuits ( timer, ltbc) keep operating states. ? stop mode: stop of low - speed oscillation and high - speed oscillation (operations of cpu and peripheral circuits are stop ped.) ? clock gear: the frequency of high - speed system clock can be changed by software (1/1, 1/2, 1/4, 1/8,1/16,1/32 of the oscillation clock) ? block control function: power down (reset registers and stop clock supply) the circuits of unused peripherals. ? shipment ? 64- pin plastic tqfp ml620q536/q538 tray ? 80- pin plastic tqfp ml620q546/q548 tray ? 100- pin plastic tqfp ml620q556/q558 tray ? guaranteed operating range ? operating temperature (ambient) : ? 40 c to +9 5 c ? operating voltage: v dd = 1.8v to 5.5v
p e dl620q 53x_ 5 4 x _5 5 x - 0 6 ml620q 53x/ 54 x / 55 x 5 /9 block diagram ml620q 536/538/ 546 /548/556/ 558/ block diagram epsw1~3 psw on - chip ice greg 0~15 alu elr1~3 lr ea sp instruction de coder instruction register escr1~3 dsr/csr pc bus controller timing controller cpu (nx - u16/100) program memory (flash) 128k/256kbyte co - processor (muldiv) power v dd v ddl v ddx reset & test reset_n t est 0 test1_n osc xt0* xt1* osc0* osc 1* lsclk* outclk* rc - adc x 2 in0* cs0* rs0* rt0* crt0* rcm* in1* cs1* rs1* rt1* v ref ain0 to ain19* ( ml620q54x/55x) ain4toain19* (ml620q53x) sa - adc cmp0p* cmp0m* cmp1p* cmp1m* analog comparator x 2 v ss ram 10k/20 kb data flash 2kb interrupt controller wdt ltbc x 2 vls int int 2 int int int 3 int lld timer 8bit x 12 int 12 tmout0 to tmout b * motor pwm 16b it x1 int pwm_u* pwm_ub* pwm_v* pwm_vb* pwm_w* pwm_wb* 1 ssio - f x2 int sckf0* sckf1* sinf0* sinf1* sou tf0* soutf1* 2 ssf0* ssf1* uart - f x4 int rxdf0 to rxdf3* txdf0 to txdf3* 4 i 2 c x2 int sda0* sda1* scl0* scl1* 2 bz* gpio int 8 rtc int high speed rc- osc (16mhz) low speed rc- osc (32.768khz) uart x1 int rxd0* 2 txd0* 3 multi - funct i on timer 16bit x8 int 8 tmcki * melody int 1 int ftmout0 to f* ftmout10 to 1f* pxt0 to pxt1 p00 to p c3 (ml620q55 x ) p 00 to p 97 (ml620q54 x ) pwm_ gb * pwm_ gblb * p00 to p 33,p40top53 p60top77,p90top97 (ml620q53x) x:6,8 * 2 nd /3 rd /4 th /5 th function
p e dl620q 53x_ 5 4 x _5 5 x - 0 6 ml620q 53x/ 54 x / 55 x 6 /9 package dimensions ml620q5 36/538 package di mensions ml620q546 /548 package dimensions
p e dl620q 53x_ 5 4 x _5 5 x - 0 6 ml620q 53x/ 54 x / 55 x 7 /9 ml620q 556/ 558 package dimensions notes for mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, conta ct a rohm sales office for the p roduct name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and tim es).
p e dl620q 53x_ 5 4 x _5 5 x - 0 6 ml620q 53x/ 54 x / 55 x 8 /9 revision history document no. date page description previous edition previous edition pe dl6 20q546_558 -01 dec.1.2013 ? ? 1st release edition pe dl6 20q546_558 -0 2 apr.24.2014 1to4 1to4 modification of features 5 5 modification of block diagram pe dl6 20q546_558 -0 3 jun.14.2014 2 2 modification of resolution of sa - adc. 3 3 modification of number of general i/o ports. 4 4 modification of function of block control 5 5 modif ication of block diagram pe dl6 20q546_558 -0 4 nov.20.2014 3 3 modification of number of general i/o ports. 4 4 modification of block diagram pe dl6 20q546_558 -0 5 apr . 30 .2015 1 to 8 1 to8 modification of general description . added package dimensions. ped l620q 53x_ 54x _55 x -0 6 jly.30.2015 1 to 8 1 to8 added ml620q536/538/548/556 information.
p e dl620q5 46_558 - 0 6 ml620q5 46 /620q5 58 9 /9 notes 1) the information contained herein is subject to change without notice. 2) although lapis semiconductor is continuously working to improve product reliability and quality, semiconductors can break down and malfunction due to various factors. therefore, in order to prevent personal injury or fire arising from failur e, please take safety measures such as complying with the derating characteristics, implementing redun dant and fire prevention designs, and utilizing backups and fail - safe procedures. lapis semiconductor shall have no responsibility for any damages arising out of the use of our products beyond the rating specified by lapis semiconductor. 3) examples of appli cation circuits, circuit constants and any other information contained herein are provided only to illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass productio n. 4) the technical information specified herein is intended only to show the typical functions of the products and examples of application circuits for the products. no license, expressly or implied, is granted hereby under any intellectual property rights or other rights of lapis semiconductor or any third party with respect to the information contained in this document; therefore lapis semiconductor shall have no responsibility whatsoever for any dispute, concerning such rights owned by third parties, ari sing out of the use of such technical information. 5) the products are intended for use in general electronic equipment (i.e. av/oa devices, communication, consumer systems, gaming/entertainment sets) as well as the applications indicated in this document. 6) the products specified in this document are not designed to be radiation tolerant. 7) for use of our products in applications requiring a high degree of reliability (as exemplified below), please contact and consult with a lapis semiconductor representative: transportation equipment (i.e. cars, ships, trains), primary communication equipment, traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and power transmission systems. 8) do not use our products in applications requiring extremely high reliability, such as aerospace equipment, nuclear power control systems, and submarine repeaters. 9) lapis semiconductor shall have no responsibility for any damages or injury arising from non - compliance with the recommended usage c onditions and specifications contained herein. 10) lapis semiconductor has used reasonable care to ensure the accuracy of the information contained in this document. however, lapis semiconductor does not warrant that such information is error - free and lapis semiconductor shall have no responsibility for any damages arising from any inaccuracy or misprint of such information. 11) please use the products in accordance with any applicable environmental laws and regulations, such as the rohs directive. for more deta ils, including rohs compatibility, please contact a rohm sales office. lapis semiconductor shall have no responsibility for any damages or losses resulting non - compliance with any applicable laws or regulations. 12) when providing our products and technologie s contained in this document to other countries, you must abide by the procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the us export administration regulations and the foreign exchange and fo reign trade act. 13) this document, in part or in whole, may not be reprinted or reproduced without prior consent of lapis semiconductor. copyright 2014 - 2015 lapis semiconductor co., ltd. 2 - 4 - 8 shinyokohama, kouhoku - ku, yokohama 222 - 8575, japan http://www.lapis - semi.com/en/
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